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d a t a sh eet product speci?cation supersedes data of 1995 mar 22 file under integrated circuits, ic02 1996 mar 20 integrated circuits TDA8766 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter
1996 mar 20 2 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 features 10-bit resolution 2.7 to 5.25 v operation sampling rate up to 20 mhz dc sampling allowed high signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 1.0 mhz full-scale input at f clk = 20 mhz) in range (ir) cmos output cmos/ttl compatible digital inputs and outputs external reference voltage regulator power dissipation only 53 mw (typical) low analog input capacitance, no buffer amplifier required standby mode no sample-and-hold circuit required. applications high-speed analog-to-digital conversion for: video data digitizing camera camcorder radio communication. general description the TDA8766 is a 10-bit high-speed analog-to-digital converter (adc) for professional video and other applications. it converts with 2.7 to 5.25 v operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 mhz. all digital inputs and outputs are cmos compatible. a standby mode allows reduction of the device power consumption down to 4 mw. quick reference data ordering information symbol parameter conditions min. typ. max. unit v dda analog supply voltage 2.7 3.3 5.25 v v ddd1 digital supply voltage 1 2.7 3.3 5.25 v v ddd2 digital supply voltage 2 2.7 3.3 5.25 v v ddo output stages supply voltage 2.5 3.3 5.25 v i dda analog supply current - 7.5 10 ma i ddd digital supply current - 7.5 10 ma i ddo output stages supply current f clk = 20 mhz; c l = 20 pf; ramp input - 12ma inl integral non-linearity f clk = 20 mhz; ramp input - 1 2 lsb dnl differential non-linearity f clk = 20 mhz; ramp input - 0.25 0.7 lsb f clk(max) maximum clock frequency 20 -- mhz p tot total power dissipation v dda =v ddd =v ddo = 3.3 v - 53 73 mw type number package name description version TDA8766g lqfp32 plastic low profile quad flat package; 32 leads; body 5 5 1.4 mm sot401-1
1996 mar 20 3 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 block diagram fig.1 block diagram. handbook, full pagewidth 19 10 14 r lad 11 15 v rb v ssa v ssd2 v sso v ssd1 v rm v rt v i 18 v ddd2 7 2 v dda 28 29 30 31 27 d4 d5 d6 d7 d8 26 25 1 6 d3 d2 23 d1 22 d0 d9 in range latch cmos outputs latches analog -to - digital converter clock driver mlc853 cmos output 5 clk 16 oe stdby TDA8766 20 v ddo 9 analog ground digital ground 2 3 21 output ground digital ground 1 analog voltage input data outputs lsb msb 4 v ddd1 ir output
1996 mar 20 4 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 pinning symbol pin description d9 1 data output; bit 9 (msb) ir 2 in range data output v ssd1 3 digital ground 1 v ddd1 4 digital supply voltage 1 (2.7 to 5.25 v) clk 5 clock input stdby 6 standby mode input v dda 7 analog supply voltage (2.7 to 5.25 v) n.c. 8 not connected v ssa 9 analog ground v rb 10 reference voltage bottom input v rm 11 reference voltage middle n.c. 12 not connected n.c. 13 not connected v i 14 analog input voltage v rt 15 reference voltage top input oe 16 output enable input n.c. 17 not connected v ddd2 18 digital supply voltage 2 (2.7 to 5.25 v) v ssd2 19 digital ground 2 v ddo 20 positive supply voltage for output stage (2.5 to 5.25 v) v sso 21 digital output ground d0 22 data output; bit 0 (lsb) d1 23 data output; bit 1 n.c. 24 not connected d2 25 data output; bit 2 d3 26 data output; bit 3 d4 27 data output; bit 4 d5 28 data output; bit 5 d6 29 data output; bit 6 d7 30 data output; bit 7 d8 31 data output; bit 8 n.c. 32 not connected symbol pin description fig.2 pin configuration. handbook, full pagewidth TDA8766 mlc854 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 index corner d9 ir v ddd1 v ssd1 v clk stdby dda v ddd2 v ssd2 v ddo v sso n.c. n.c. d1 d0 n.c. n.c. d8 d7 d6 d5 d4 d3 d2 ssa n.c. n.c. oe v rb v rm v i v rt v
1996 mar 20 5 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. the supply voltages v dda , v ddd and v ddo may have any value between - 0.3 v and +7.0 v provided that the supply voltage differences d v dd are respected. handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal characteristics symbol parameter conditions min. max. unit v dda analog supply voltage note 1 - 0.3 +7.0 v v ddd1 , v ddd2 digital supply voltages note 1 - 0.3 +7.0 v v ddo output stages supply voltage note 1 - 0.3 +7.0 v d v dd supply voltage difference v dda - v ddd - 1.0 +4.0 v v ddd - v ddo - 1.0 +4.0 v v dda - v ddo - 1.0 +4.0 v v i input voltage referenced to v ssa - 0.3 +7.0 v v clk(p-p) ac input voltage for switching (peak-to-peak value) referenced to v ssd - v ddd v i o output current - 10 ma t stg storage temperature - 55 +150 c t amb operating ambient temperature - 20 +75 c t j junction temperature - +150 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 90 k/w
1996 mar 20 6 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 characteristics v dda =v 7 to v 9 = 3.3 v; v ddd =v 4 to v 3 =v 18 to v 19 = 3.3 v; v ddo =v 20 to v 21 = 3.3 v; v ssa ,v ssd and v sso short-circuited together; v i(p-p) = 1.83 v; c l = 20 pf; t amb =0to+70 c; typical values measured at t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dda analog supply voltage 2.7 3.3 5.25 v v ddd1 digital supply voltage 1 2.7 3.3 5.25 v v ddd2 digital supply voltage 2 2.7 3.3 5.25 v v ddo output stages supply voltage 2.5 3.3 5.25 v d v dd voltage difference v dda - v ddd - 0.2 - +0.2 v v dda - v ddo - 0.2 - +3.0 v v ddd - v ddo - 0.2 - +3.0 v i dda analog supply current - 7.5 10 ma i ddd digital supply current - 7.5 10 ma i ddo output stages supply current f clk = 20 mhz; ramp input; c l =20pf - 12 ma inputs c lock input clk ( referenced to v ssd ); see note 1 v il low level input voltage 0 - 0.3v ddd v v ih high level input voltage 0.7v ddd - v ddd v v ddd 3.6 v 0.6v ddd - v ddd v i il low level input current v clk = 0.3v ddd - 10+1 m a i ih high level input current v clk = 0.7v ddd -- 5 m a z i input impedance f clk = 20 mhz - 4 - k w c i input capacitance f clk = 20 mhz - 3 - pf i nputs oe and stdby ( referenced to v ssd ); see table 3 v il low level input voltage 0 - 0.3v ddd v v ih high level input voltage 0.7v ddd - v ddd v v ddd 3.6 v 0.6v ddd - v ddd v i il low level input current v il = 0.3v ddd - 1 -- m a i ih high level input current v ih = 0.7v ddd -- +1 m a v i ( analog input voltage referenced to v ssa ) i il low level input current v i =v rb - 0 -m a i ih high level input current v i =v rt - 35 -m a z i input impedance f i = 1 mhz - 5 - k w c i input capacitance f i = 1 mhz - 8 - pf
1996 mar 20 7 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 reference voltages for the resistor ladder; see table 1 v rb reference voltage bottom 1.1 1.2 - v v rt reference voltage top v top v dda 2.7 3.3 v dda v v diff differential reference voltage v rt - v rb 1.5 2.1 2.7 v i ref reference current - 7.2 - ma r lad resistor ladder - 290 -w tc rlad temperature coef?cient of the resistor ladder - 1860 - ppm - 539 - m w /k v osb offset voltage bottom note 2 - 135 - mv v ost offset voltage top note 2 - 135 - mv v i(p-p) analog input voltage (peak-to-peak value) note 3 1.4 1.83 2.4 v outputs d igital outputs d9 to d0 and ir ( referenced to v ssd ) v ol low level output voltage i o =1ma 0 - 0.5 v v oh high level output voltage i o = - 1ma v ddo - 0.5 - v ddo v i oz output current in 3-state mode 0. 5v 1996 mar 20 8 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 notes 1. in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. 2. analog input voltages producing code 0 up to and including 1023: a) v osb (voltage offset bottom) is the difference between the analog input which produces data equal to 00 and the reference voltage bottom (v rb ) at t amb =25 c. b) v ost (voltage offset top) is the difference between v rt (reference voltage top) and the analog input which produces data outputs equal to 1023 at t amb =25 c. 3. in order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins v rb and v rt via offset resistors r ob and r ot as shown in fig.3. a) the current flowing into the resistor ladder is i l = and the full-scale input range at the converter, to cover code 0 to code 1023, is b) since r l , r ob and r ot have similar behaviour with respect to process and temperature variation, the ratio will be kept reasonably constant from part to part. consequently variation of the output codes at a given input voltage depends mainly on the difference v rt - v rb and its variation with temperature and supply voltage. when several adcs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. e ffective bits ; see fig.9; note 5 eb effective bits f clk = 20 mhz f i = 300 khz - 9.5 - bits f i = 1 mhz - 9.3 - bits f i = 3.58 mhz - 8.0 - bits timing (f clk = 20 mhz; c l = 20 pf); see fig.4; note 6 t ds sampling delay time -- 5ns t h output hold time 5 -- ns t d output delay time v ddo = 4.75 v 8 12 15 ns v ddo = 3.15 v 8 17 20 ns v ddo = 2.7 v 8 21 24 ns 3-state output delay times; see fig.5 t dzh enable high - 14 18 ns t dzl enable low - 16 20 ns t dhz disable high - 16 20 ns t dlz disable low - 14 18 ns standby mode output delay times t dstblh standby (low-to-high transition) -- 200 ns t dstbhl start-up (high-to-low transition) -- 500 ns symbol parameter conditions min. typ. max. unit v rt v rb C r ob r l r ot ++ ----------------------------------------- - v i r l i l r l r ob r l r ot ++ ----------------------------------------- - v rt v rb C () 0.871 v rt v rb C () = = = r l r ob r l r ot ++ -----------------------------------------
1996 mar 20 9 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 4. the analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 5. effective bits are obtained via a fast fourier transform (fft) treatment taking 8k acquisition points per equivalent fundamental period. the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conversion to signal-to-noise ratio: s/n = eb 6.02 + 1.76 db. 6. output data acquisition: the output data is available after the maximum delay time of t d . fig.3 explanation of note 3. handbook, halfpage r lad r ot v rt v rm v rb r ob code 1023 code 0 mgd281 i l r l
1996 mar 20 10 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 table 1 output coding and input voltage (typical values; referenced to v ssa ) table 2 mode selection table 3 standby selection step v i(p-p) (v) ir binary output bits d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 under?ow < 1.335 00000000000 0 1.335 10000000000 1 . 10000000001 . . ........... . . ........... 1022 . 11111111110 1023 3.165 11111111111 over?ow > 3.165 01111111111 oe d9 to d0 ir 1 high impedance high impedance 0 active; binary active stdby d9 to d0 i dda +i ddd (typ.) 1 last logic state 1.2 ma 0 active 15 ma fig.4 timing diagram. handbook, full pagewidth ds t sample n + 1 sample n clk mgd346 sample n + 2 50% v l data d0 to d9 t d t h cph t cpl t v ddo 0 v 50% data n + 1 data n data n - 1 data n - 2
1996 mar 20 11 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 fig.5 timing diagram and test conditions of 3-state output delay time. f oe = 100 khz. handbook, full pagewidth mlc855 50 % 50 % high low dzh t dhz t 50 % high low dzl t dlz t 10 % 90 % output data v ddd output data 3.3 k w 20 pf s1 v ddd TDA8766 oe oe test dlz t dzl t dhz t dzh s1 ddd v ddd v gnd gnd t
1996 mar 20 12 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 fig.6 typical integral non-linearity (inl) performance. handbook, full pagewidth 1023 - 0.6 0 400 600 800 1000 1100 200 mld115 0.4 - 0.2 - 0.4 0.2 0 0.6 a (lsb) f (codes) fig.7 typical differential non-linearity (dnl) performance. handbook, full pagewidth 1023 - 0.25 0 400 600 800 1000 1100 200 mld116 0.25 - 0.05 - 0.15 0.15 0.05 a (lsb) f (codes)
1996 mar 20 13 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 fig.8 analog input settling-time diagram. handbook, full pagewidth mbd875 50 % stlh t 5 ns code 0 code 1023 i 50 % 2 ns 50 % 5 ns sthl t 50 % 2 ns clk v fig.9 typical fast fourier transform (f clk = 20 mhz; f i = 1 mhz). effective bits: 9.59; thd = - 76.60 db. harmonic levels (db): 2nd = - 81.85; 3rd = - 87.56; 4th = - 88.81; 5th = - 88.96; 6th = - 79.58. handbook, full pagewidth 10 0 120 0 2.5 3.76 5.01 7.51 8.76 1.25 6.26 mld117 40 80 100 60 20 a (db) f (mhz)
1996 mar 20 14 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 internal pin configurations fig.10 cmos data and in range (ir) outputs. handbook, halfpage mlc856 v ddo v d9 to d0 ir sso fig.11 analog inputs. handbook, halfpage mlc857 v dda v ssa v i fig.12 oe (stdby) input. handbook, halfpage mlc858 v ddo v sso oe (stdby) fig.13 v rb , v rm and v rt . handbook, halfpage r mlc859 v rb v rm v dda v ssa v rt lad
1996 mar 20 15 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 fig.14 clk input. handbook, halfpage v ddd v ssd clk mlc860 1 / 2 v ddd
1996 mar 20 16 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 application information additional application information will be supplied upon request (please quote number an96012 ). fig.15 application diagram. the analog and digital supplies should be separated and decoupled. the external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respec t to the lsb value. eventually, the reference ladder voltages can be derived from a well regulated v dda supply through a resistor bridge and a decoupled capacitor. (1) v rb , v rm and v rt are decoupled to v ssa . (2) pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence. (3) when v rm is not used, pin 11 can be left open, avoiding the decoupling capacitor. in any case, pin 11 must not be grounded. (4) when analog input signal is ac coupled, an input bias or a clamping level must be applied to v i input (pin 14). handbook, full pagewidth TDA8766 mlc861 1 2 3 4 24 23 22 21 20 19 18 17 9 d9 ir v ddd1 v ssd1 v clk stdby dda v ssa v ssa v ddd2 v ssd2 v ddo v sso n.c. d1 d0 n.c. 5 6 7 8 10 v rb 11 v rm 12 13 14 v i 15 v rt 16 oe (2) n.c. (2) n.c. (2) (1) (3) (4) (1) (1) (2) n.c. (2) 100 nf v ssa 100 nf v ssa 100 nf 32 31 30 29 28 27 26 25 d5 d4 d3 n.c. (2) d2 d8 d7 d6
1996 mar 20 17 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 package outline 0.2 unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 0.5 7.15 6.85 1.0 0.95 0.55 7 0 o o 0.12 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot401-1 95-12-19 97-08-04 d (1) (1) (1) 5.1 4.9 h d 7.15 6.85 e z 0.95 0.55 d b p e e b 8 d h b p e h v m b d z d a z e e v m a x 1 32 25 24 17 16 9 q a 1 a l p detail x l (a ) 3 a 2 y w m w m 0 2.5 5 mm scale lqfp32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm sot401-1 c pin 1 index
1996 mar 20 18 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering lqfp packages lqfp48 (sot313-2), lqfp64 (sot314-2) or lqfp80 (sot315-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 mar 20 19 philips semiconductors product speci?cation 10-bit high-speed 2.7 to 5.25 v analog-to-digital converter TDA8766 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
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(0212) 282 6707 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. 380-44-4760297, fax. 380-44-4766991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181) 730-5000, fax. (0181) 754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800) 234-7381, fax. (708) 296-8556 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. (381) 11 825 344, fax. (359) 211 635 777 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31-40-2724825 scds48 ? philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 537021/1100/02/pp20 date of release: 1996 mar 20 document order number: 9397 750 00746

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